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Freescale Semiconductor /MK80F25615 /FLEXIO0 /TIMCFG2

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Interpret as TIMCFG2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)TSTART 0 (00)TSTOP 0 (000)TIMENA 0 (000)TIMDIS 0 (000)TIMRST 0 (00)TIMDEC 0 (00)TIMOUT

TIMDEC=00, TSTOP=00, TSTART=0, TIMOUT=00, TIMDIS=000, TIMRST=000, TIMENA=000

Description

Timer Configuration N Register

Fields

TSTART

Timer Start Bit

0 (0): Start bit disabled

1 (1): Start bit enabled
TSTOP

Timer Stop Bit

0 (00): Stop bit disabled

1 (01): Stop bit is enabled on timer compare

2 (10): Stop bit is enabled on timer disable

3 (11): Stop bit is enabled on timer compare and timer disable
TIMENA

Timer Enable

0 (000): Timer always enabled

1 (001): Timer enabled on Timer N-1 enable

2 (010): Timer enabled on Trigger high

3 (011): Timer enabled on Trigger high and Pin high

4 (100): Timer enabled on Pin rising edge

5 (101): Timer enabled on Pin rising edge and Trigger high

6 (110): Timer enabled on Trigger rising edge

7 (111): Timer enabled on Trigger rising or falling edge
TIMDIS

Timer Disable

0 (000): Timer never disabled

1 (001): Timer disabled on Timer N-1 disable

2 (010): Timer disabled on Timer compare

3 (011): Timer disabled on Timer compare and Trigger Low

4 (100): Timer disabled on Pin rising or falling edge

5 (101): Timer disabled on Pin rising or falling edge provided Trigger is high

6 (110): Timer disabled on Trigger falling edge
TIMRST

Timer Reset

0 (000): Timer never reset

2 (010): Timer reset on Timer Pin equal to Timer Output

3 (011): Timer reset on Timer Trigger equal to Timer Output

4 (100): Timer reset on Timer Pin rising edge

6 (110): Timer reset on Trigger rising edge

7 (111): Timer reset on Trigger rising or falling edge
TIMDEC

Timer Decrement

0 (00): Decrement counter on FlexIO clock, Shift clock equals Timer output.

1 (01): Decrement counter on Trigger input (both edges), Shift clock equals Timer output.

2 (10): Decrement counter on Pin input (both edges), Shift clock equals Pin input.

3 (11): Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
TIMOUT

Timer Output

0 (00): Timer output is logic one when enabled and is not affected by timer reset

1 (01): Timer output is logic zero when enabled and is not affected by timer reset

2 (10): Timer output is logic one when enabled and on timer reset

3 (11): Timer output is logic zero when enabled and on timer reset

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data